High Performance Reconfigurable Computing
High-performance reconfigurable computing (HPRC) combines the computing power of conventional microprocessors with the flexibility of the configurable fabric of field-programmable gate arrays (FPGAs). Most HPRCs are computers with microprocessors that can be used in traditional CPU cluster computers with a close coupling to user-programmable FPGAs for hybrid computing. In this configuration, FPGAs are typically used as co-processors for specific functions.
Most HPRCs achieve reconfiguration through either HDL or C-based languages. Another approach is to have a C-to-Gates compiler with the idea that the same C code can run on a processor or an FPGA depending on resources available.
The most important factor in HPRC efficiency is host coupling. Often the reconfigurable array is used as a processing accelerator attached to a host processor. The level of coupling determines the type of data transfers, latency, power, throughput and overheads involved when utilizing the reconfigurable logic.