The Arches-MPI Design Kit consists of the Arches-MPI software libraries for the Xilinx MicroBlaze and x86 processor, the Arches-MPE FPGA-based message-passing engine and Arches-MPI networking components including the FSB interface. The kit currently supports the Xilinx Accelerated Computing Platform and the Nallatech FPGA-FSB modules using Xilinx Virtex-5 FPGAs. The kit also includes supporting applications that help with configuring the MPI-network and building and launching the application.
The Arches-MPI Development Platform is a development kit that combines the Xilinx Accelerated Computing Platform and the Nallatech FSB-FPGA modules with the Arches-MPI Design Kit. It can be used for quickly realizing the power of heterogeneous embedded processing using Arches-MPI. Please see our Arches-MPI Product Brochure or contact us for more information.
The Arches Full-Duplex LVDS Interface is a 10 Gbps to 40 Gbps LVDS Transceiver for Xilinx Virtex-5TM and Virtex-6TM FPGAs, providing designers with a flexible, easy-to-use method of connecting two FPGAs using a high-speed parallel LVDS bus. Industry-standard link speeds of 10Gbps and 40Gbps can be sustained using minimal I/O resources:
The core includes circuitry for clock forwarding, detection and recovery, serialization and de-serialization of parallel data, automatic training and alignment of data busses, flow control, clock domain crossing, as well as automatic link renegotiation if a link partner is reset, reprogrammed or hot-swapped. Users are presented with an abstracted low-latency synchronous FIFO interface of configurable width to exchange data with link partners. The design can be instantiated within an ISE design as a macro or as part of an EDK system as a PCORE.
Please see our LVDS Full Product Feature Sheet or Contact Us for more information.